1. Field of Invention
The present invention relates to a method of operating a memory cell, and more generally to a method of operating a vertical memory cell.
2. Description of Related Art
A memory is a semiconductor device designed for storing information or data. As the functions of computer microprocessors become more and more powerful, programs and operations executed by software are increasing correspondingly. Consequentially, the demand for high storage capacity memories is getting more. Among various types of memory products, a non-volatile memory such as an electrically erasable programmable read only memory (EEPROM) allows multiple-time data programming, reading and erasing operations, and the data stored therein can be retained even after the power of the memory is interrupted. With these advantages, EEPROM has become one of the most widely adopted memories for personal computers and electronic equipment.
Typical EEPROM is composed of a floating gate and a control gate, which are made of doped polysilicon. When the memory is programmed, the electrons injected into the floating gate uniformly distributes in the polysilicon floating gate. However, when defects exist in the tunnel oxide layer under the polysilicon floating gate, a leakage is easily generated in the device, and the reliability of the device is decreased.
In order to solve the leakage problem of the EEPROM, one known method is adopting a stacked gate structure including a non-conductive charge-storage layer instead of the polysilicon floating gate. Another advantage obtained from replacing the polysilicon floating gate with the charge-storage layer is that the electrons are only stored in a portion of the charge-storage layer over the channel region adjacent to the source region or drain region while the device is programmed. Therefore, during the programming process, the voltages can be applied to the source region and the control gate respectively. Hence, the electrons are stored in a portion of the charge-storage layer near the drain region with a form of Gaussian distribution. Alternatively, the voltages can be applied to the drain region and the control gate respectively. Hence, the electrons are stored in a portion of the charge-storage layer near the source region with a form of Gaussian distribution. In the other words, there are two storage regions in the charge-storage layer. By properly applying the voltages to the control gate and to either the source region or the drain region, there can be four different storage states, which includes each of the storage regions having one group of electrons with a Gaussian distribution property, either one of the storage regions having one group of electrons with a Gaussian distribution property and none of the electrons stored in both storage regions, in the charge-storage layer. That is, a single flash memory cell can present four different storage states. Hence, instead of using the floating gate, the flash memory with a charge-storage layer is considered a 2-bit-per-cell memory.
In order to increase the number of bits of a memory cell, a memory structure with a vertical memory cell is developed. This kind of memory cell is a 4-bit-per-cell flash memory. However, in the memory structure with the vertical memory cell, when the selected bit is programmed, interference to other bits is generated by the conventional technique. Therefore, the selected bit and non-selected bits are indistinguishable, so that the purpose of storing multiple bits is hardly achieved.